ρ-VEX
For my Master's thesis project at the Computer Engineering Laboratory at Delft University of Technology I designed and implemented an open source reconfigurable and extensible VLIW processor. My work was part of the research conducted for the Molen reconfigurable processing paradigm. My project was graded with a 9.0 out of 10 by the University, and was published and presented on ICFPT 2008 in Taipei, Taiwan.
About
ρ-VEX is an open source reconfigurable and extensible Very-Long Instruction Word (VLIW) processor, accompanied by a development framework consisting of a VEX assembler, ρ-ASM. The processor architecture is based on the VEX ISA, as introduced by J.A. Fisher et al. The VEX ISA offers a scalable technology platform for embedded VLIW processors that allows variation in many aspects, including instruction issue-width, organization of functional units, and instruction set. ρ-VEX is designed in VHDL, and the prototype ran on several Field-Programmable Gate Arrays (FPGAs). ρ-ASM was written in C.
Architecture
The VEX ISA was chosen for this project, because it has a scalable design based on the Lx processors by HP and ST Microelectronics, and a good compiler was available. No known hardware implementations existed at the time of the project. The VEX ISA allows for clusters of processors, that each have their own extensible ISA. Below is a schematic overview of the default configuration for the ρ-VEX processor. The 'execute' stage contains 4 ALUs, and 2 MULtiplier units. As mentioned before, this is all parameterizable.
ρ-VEX has support for reconfigurable operations, ρ-OPS. These are operations that can be described in a separate hardware description, and 'loaded' into the processor's current opcode space. There is space for a number of ρ-OPS for each ρ-VEX instance. At the time of the prototype, ρ-OPS could not be changed or loaded at runtime. The whole toolchain, including the VEX compiler by HP and ρ-ASM support these custom operations. The schematic below shows the development toolchain.
The source code for both &rho-VEX and &rho-ASM, as well as a lot of prototype documentation can be downloaded from the project page at r-vex.googlecode.com. Currently, research on ρ-VEX is still actively being conducted by different universities.
My supervisor for this project was Dr.ir. S. Wong (Delft University of Technology), and my advisor was Prof. G. Brown (Indiana University).
Documents
Thijs van As Master's Thesis, September 2008 |
Stephan Wong, Thijs van As & Geoffrey Brown IEEE International Conference on Field Programmable Technologies (ICFPT), December 2008 |
Thijs van As Master's Thesis Defense Slides, September 2008 |
Thijs van As Source code snapshot, September 2008 |
References to ρ-VEX
ρ-VEX has been referenced or cited in multiple other publications. Here's an overview of known references:
- F. Anjam, S. Wong, M.F. Nadeem, A shared Reconfigurable VLIW Multiprocessor System, 17th Reconfigurable Architecture Workshop (RAW 2010), Atlanta, Geogia, USA, April 2010
- S. Wong, F. Anjam, M.F. Nadeem, Dynamically Reconfigurable Register File for a Softcore VLIW Processor, Proceedings of the Design, Automation and Test in Europe Conference (DATE 2010), Dresden, Germany, March 2010
- N. Moser, S. Hauser, C. Gremzow, A Hybrid Transport/Control Operation Triggered Architecture, 23th International Conference on Architecture of Computing Systems 2010, ARCS '10, February 2010
- S. Wong, F. Anjam, The Delft Reconfigurable VLIW Processor, 17th International Conference on Advanced Computing and Communications (ADCOM 2009), pp. 244-251, Bangalore, India, December 2009
- F. Mayer-Lindenberg, High-Level FPGA Programming through Mapping Process Networks to FPGA Resources, International Conference on Reconfigurable Computing and FPGAs, 2009. ReConFig '09, December 2009
- C.S. Bassoy, H. Manteuffel, F. Mayer-Lindenberg, Sharf: An FPGA-based customizable processor architecture, International Conference on Field Programmable Logic and Applications, 2009. FPL 2009, September 2009