ρ-VEX
Description
For my MSc project at the Computer Engineering Laboratory at Delft Universitiy of Technology I designed and implemented a reconfigurable Very Large Instruction Word (VLIW) processing core (ρ-VEX), for the use within the Molen reconfigurable processing paradigm. The Instruction Set Architecture (ISA) used for this processing core is VEX (VLIW Example), which is loosely modeled on the ISA of the HP/ST Lx family of VLIW embedded cores.
Documents
- ρ-VEX: A Reconfigurable and Extensible VLIW Softcore Processor
- Type: Paper
- Authors: Stephan Wong, Thijs van As and Geoffrey Brown
- Publication: IEEE International Conference on Field Programmable Technologies (ICFPT) 2008
- Date: December 2008
- ρ-VEX: A Reconfigurable and Extensible VLIW Processor
- Type: MSc Thesis
- Authors: Thijs van As
- Date: September 2008
- ρ-VEX: A Preliminary Performance And Configuration Analysis
- Type: Paper
- Authors: Thijs van As, Stephan Wong and Geoffrey Brown
- Date: February 2008
- ρ-VEX: A Parameterizable and Reconfigurable VLIW Processor Core for MOLEN
- Type: Project Schedule
- Authors: Thijs van As
- Date: December 2007
Details
- Author: Thijs van As
- Supervisor: Dr.ir. S. Wong (Delft University of Technology)
- Advisor: Prof. G. Brown (Indiana University)
- Date: Dec 2007 - Sept 2008
- Grade: 9 out of 10
- Website: http://r-vex.googlecode.com