• ρ-VEX
  • Author: Thijs van As
  • Supervisor: Dr.ir. S. Wong (Delft University of Technology)
  • Advisor: Prof. G. Brown (Indiana University)
  • Date: Dec 2007 - Sept 2008
  • Grade: 9 out of 10
  • Website: visit

• Project HELIOS
  • Authors: Thijs van As & Siebe Krijgsman
  • Lanuage: VHDL / C
  • Tested on: Digilent XUP-V2P board (with Xilinx Virtex 2 Pro FPGA)
  • Date: April-June 2006
  • Course: Bachelor's project Electrical Engineering
  • Status: Out of development
  • Description: We built a live video capturer on a XUP-V2P development board. An IP core of Xilinx was used, and controlled by an embedded PowerPC CPU in the FPGA fabric. Software for the CPU was written in C. The capturer was able to capture and store live video data in PAL and NTSC format. Storing was possible on a Compact Flash card or streaming over an ethernet. Graded 9/10.

Reconfigurable Computing

• ρ-VEX: A Reconfigurable and Extensible VLIW Softcore Processor
  • Authors: Stephan Wong, Thijs van As and Geoffrey Brown
  • Publication: IEEE International Conference on Field Programmable Technologies (ICFPT) 2008
  • Date: December 2008

• ρ-VEX: A Preliminary Performance And Configuration Analysis
  • Authors: Thijs van As, Stephan Wong & Geoffrey Brown
  • Date: February 2008

• Reconfigurable Architectures: A Survey of Design and Implementation Methods
  • Authors: Thijs van As & Siebe Krijgsman
  • Date: July 2007

• Microprocessor Soft-Cores: An Evaluation of Design Methods and Concepts on FPGAs
  • Authors: Thijs van As & Pieter Anemaet
  • Date: June 2007

Spartan-3E Starter Kit

• IP core for on-board LCD
  • Author: George Wang
  • Original website: visit
  • Modified by: Thijs van As
  • Language: VHDL
  • EDK Compatibility: 8.1
  • Status: Out of development
  • Description: I modified and stripped this IP core by George Wang so that it is easily imported in an EDK project by the Create/Import Peripheral method. The original IP core made directly used of the output pins connected to the on board LEDs. This is decoupled, so that you can use your LEDs still as GPIO devices, and enable them through the Base System Builder. It now directly inserts a C library in your project, so that the LCD can be used in all your MicroBlaze projects. The software demo made by George Wang is included, as well as a demo by myself which also uses an UART.

General

• Universal Asynchronous Receiver/Transmitter (UART)
  • Author: Thijs van As
  • Lanuage: VHDL
  • Tested on: Spartan-3E Starter Kit, XST 8.1
  • Description: A UART with separate transmitter and receiver modules. Works on 115k2 bps by default (8 bits of data, no parity bit). The settings can however be adapted without much work. I'm currently working on a debugging framework which incorporates this UART core.

• Arkanoid/Breakout
  • Author: Thijs van As
  • Lanuage: VHDL
  • Tested on: Spartan-3E Starter Kit, XST 8.1 & 9.1
  • Screens: YouTube
  • Description: An Arkanoid paddle game clone in VHDL. It uses an RGB VGA interface for output. Currently has some issues with grids of blocks larger than 3x3. Will look after that when I have time.

• Monophonic jukebox
  • Author: Thijs van As
  • Lanuage: VHDL
  • Tested on: Spartan-3E Starter Kit, XST 9.1
  • Screens: YouTube
  • Status: In development
  • Description: A jukebox developed in hardware, uses a frequency generator with variable output, a note to frequency converter and a sequencer. Currently a demo is ready featuring Dream Theater's In The Presence of Enemies intro.

• G.723 Audio co-Processor
  • Author: Thijs van As, Siebe Krijgsman
  • Lanuage: VHDL, C, ATmega102 assembly
  • Report: here
  • Course: VLSI Systems on Chip
  • Description: A hardware implementation of a G.723 audio compression/decompression co-processor for an Atmel AVR ATmega103 CPU. Communication between the ATmega and the co-processor is implemented via a Whisbone bus. The core features both 24 and 40 kbps sample rates as well as u-law, A-law and linear coding. Graded 9/10.

Other projects (in larval stage or future projects)

• Debug-Over-UART framework
• MicroBlaze based embedded IRC client

x86

• BOPS 32 bit (MIPS) RISC simulator extended with floating point instructions
  • Author: Dr. B.H.H. Juurlink
  • Original website: visit
  • Modified by: Thijs van As & Pieter Anemaet
  • Report: here
  • Language: C
  • Course: Modern Computer Architectures
  • Description: The BOPS MIPS32 RISC simulator written by Dr. Juurlink was not capable of executing floating point operations. We extended the BOPS design with some floating point operations. Graded 9/10.

Other architectures

• The Sieve of Eratosthenes
  • Authors: Thijs van As & Pieter Anemaet
  • Report: here
  • Language: MIPS64 assembly
  • Course: Modern Computer Architectures
  • Description: A MIPS64 assembly implementation of the Sieve of Eratosthenes. The sieve is used to find all prime numbers up to a given integer. For the course, one 'straight-forward' implementation of the algorithm had to be implemented, and one optimized implementation, making use of loop unrolling, rescheduling etc. This was the fastest and most efficient implementation of the year, which resulted in a grade of 10/10.

General

• Blogspot/Blogger blog post fetcher
  • Author: Thijs van As
  • Language: PHP
  • Requirements: PHP >= 5 with SimpleXML extension
  • Description: A simple PHP script that fetches blog entries from a Blogger/Blogspot weblog, and outputs them in a simple HTML layout. This script is used on blog.pretopia.net.

• Brute-force sudoku solver
  • Author: Thijs van As
  • Language: PHP
  • Description: A brute-force solver for sudoku puzzles. This script is used on the sudoku page.